Manufacturers of computer memory devices are ever in pursuit of smaller geometries with increased capacity at less cost. To this end, components of memory cells are commonly layered on top of each other to create 3D stacks.
Often, formation of these 3D memory stacks begins by alternating layers of a dielectric material and a conductive material, where the conductive material layer serves as the control gate for the transistors used in the memory cells of the flash memory. Polysilicon can be used as the conductive material, but using polysilicon presents problems such as polysilicon recess, silicidation, and wet stripping of metals.
Alternatively, formation of these 3D memory stacks may begin by alternating between a dielectric layer and a charge trapping layer, such as an oxide layer followed by a nitride layer. Silicon nitride can be used as the charge trapping material, but using silicon nitride as one of the initial layers in the stack presents the problem of nitride removal with defect control. Subsequently, metals, such as tungsten, or metallic compounds, such as titanium nitride, must generally be deposited in holes or channels formed in the stack, and conformal deposition of these metals or metallic compounds presents further challenges.
Therefore, a need exists for improved methods for 3D memory structures.